1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method form forming a triple well structure.
2. Description of the Related Art
Conventional DRAM process commonly utilizes a twin well structure. The twin well includes a P-well, which is often used for forming a memory region and an N-type MOS, and an N-well, which is used for forming a P-type MOS. However, in an embedded DRAM, a memory region and a logical region are incorporated in the same wafer. Since the memory region and the logical region are supplied with different back bias, in order to prevent bias interference between the logical region and the memory region, a third well must be formed to isolate these two regions from each other. Therefore, it is desired to form the third well, such as a deep well, in the substrate to isolate the logical region and the memory region.
A conventional embedded DRAM memory region having a triple well is formed on a P-type substrate. A transistor is located in the P-type substrate. The transistor comprises an N-type gate and N-type source/drain regions. The N-type gate is formed on the P-type substrate. The N-type source/drain regions are formed within the substrate beside the N-type gate. A bit line contact would be formed on the N-type source region.
A P-type field is located in the P-type substrate under the transistor. A deep N-well is formed in the P-type substrate under the P-type field. An isolation N-well is formed around the P-type field. A bottom portion of the isolation N-well overlaps with a side portion of the deep N-well. The isolation N-well and the deep N-well together surround a portion of the P-type substrate, which is employed as a P-well. The isolation N-well, the P-well, and the deep N-well together form a triple well structure.
A method of forming the conventional triple well structure is described as follow and shown in FIGS. 1A-1C. Referring to FIG. 1A, a photoresist layer 102 is formed over a provided P-type substrate 100. The photoresist layer 102 has an opening exposing a part of the substrate 100. A first ion implantation process I1 is performed to formed a deep N-well 104 in the substrate 100.
Referring to FIG. 1B, the photoresist layer 102 is removed. A photoresist layer 106 is formed on the substrate 100. The photoresist layer 106 has an opening exposing a part of the substrate 100 located above a portion of the deep N-well 104. A second ion implantation process I2 is performed to formed an isolation N-well 108 above the deep N-well 104. The bottom portion of the isolation N-well 108 overlaps with a side of the deep N-well 104.
Referring to FIG. 1C, the photoresist layer 106 is removed. Another photoresist layer 112 is formed on the substrate 100 exposing a portion of the substrate 100 located over the deep N-well 104. A third ion implantation process I3 is performed to form a P-well 114 in the substrate 100. The deep N-well 104 and the isolation N-well 108 surround the P-well 114. A triple well structure is thus formed.
The conventional method described above requires forming three photoresist layers and performing three photolithography processes. For semiconductor fabrication, using more photoresist layers would increase complex level of fabrication. Furthermore, misalignment deviation would be increased.
The invention provides a method for forming a triple well structure. One photoresist layer is omitted so that the fabrication for forming the triple well structure becomes easier. Misalignment deviation for using different photoresist layers also can be decreased.
The method of the invention is applied on a provided substrate having a first conductive type. A first photoresist layer is formed on the substrate. A first ion implantation process is performed to form a first well, which has the first conductive type but a dopant concentration of the first well is higher than a dopant concentration of the substrate. The first photoresist layer is baked so that the volume of the first photoresist layer is decreased and the opening pattern of the first photoresist layer is thus expanded. A second ion implantation process is performed according to the expanded opening of the baked first photoresist layer to form a first doped region under the first well. The first doped region has a second conductive type. The first photoresist layer is removed. After removing the first photoresist layer, a second photoresist layer is formed on the substrate. A portion of the substrate is exposed. A third ion implantation process is performed to form a second doped region in the substrate around the first well and to form a second well in the substrate. The second doped region and the second well have the second conductive type. The second doped region and the first doped region together surround the first well. The first doped region, the first well, and the second doped region compose a triple well structure.
The invention performs a baking step to expand the opening pattern of the first photoresist layer and performs the second ion implantation process according to the expanded opening pattern. One photoresist layer can be omitted so that the fabrication of the invention is easier than a conventional fabrication of a triple well structure.